There is an ever present demand for analog to digital (A/D) converters that accurately convert an analog voltage signal into a digital representation. There is also a need for faster A/D converters that use less power and have smaller areas on an integrated circuit. Oftentimes, a conventional A/D converters sacrifice accuracy in favor of meeting speed, power consumption and size demands.
FIG. 1 illustrates a conventional pipeline analog to digital (A/D) converter 10. The A/D converter 10 converts an analog electrical input signal (V.sub.IN) into a digital representation of the analog signal (D.sub.OUT) The illustrated example is a 4-bit A/D converter, but it should be understood that a resolution of more or less bits may be implemented with the addition or removal of converter stages. Therefore, the resolution of the A/D converter will sometimes be referred to an N-bit A/D converter, where N represents the number of digital output bits. The A/D converter 10 has an analog signal input 12 provided on an initial stage. The initial stage is a sample-and-hold amplifier (SHA) 14. The SHA 14 samples the analog input signal and holds the sampled voltage, or V.sub.s/h, for the next stage of the pipeline A/D converter 10 at an SHA output 16. The stage following the SHA 14 is a multiplying digital to analog converter (MDAC) 18. MDAC 18 stages are added to the pipeline to increase the number of output bits.
With additional reference to FIG. 2, each MDAC 18 has an analog input 20 and an analog output 22. Each MDAC 18 performs analog to digital conversion of an MDAC input signal, V.sub.I, applied to the analog input 20. Each MDAC 18 also calculates an amplified residue signal, V.sub.res, which is output for the next stage at the analog output 22. The number of MDAC 18 stages is determined by the desired resolution of the A/D converter 10, or the value of N. The number of MDAC 18 stages is equal to N minus two. In the example, the resolution is four bits. Therefore there are two MDAC 18 stages, referred to as MDAC, (reference numeral 24) and MDAC.sub.2 (reference numeral 26). The SHA output 16 is connected to the analog input 20 of MDAC.sub.1. The analog output 22 of MDAC.sub.1 is connected to the analog input 20 of MDAC.sub.2. Therefore, the V.sub.I of each MDAC 20, other than MDAC.sub.1 which receives V.sub.s/h, is the V.sub.res of the preceding MDAC 18, also referred to herein as V.sub.resm where m stands for the MDAC 18 generating the output signal.
The analog output 22 of the last MDAC 18, which is MDAC.sub.2 in the example, is connected to an input 28 of a last stage 30. The last stage 30, which will be discussed in more detail below, has no analog output.
Each MDAC 18 and the last stage has two digital outputs 32, 34 for providing one bit of resolution and one bit for correcting error. The bits are generically referred to as b.sub.1 and b.sub.0 or, for a specific MDAC 18, are referred to as b.sub.m1 and b.sub.m0 where m stands for the MDAC 18 generating the output signal or the last stage 30. It is noted that MDAC.sub.1 generates b.sub.11 and b.sub.10 with some degree of error, MDAC.sub.2 generates b.sub.21 and b.sub.20 with some degree of error and so forth. With additional reference to FIG. 4, the last stage 30 of the illustrative four bit A/D converter 10 generates b.sub.3, and b.sub.31 where b.sub.30, is the least significant bit (LSB) and b.sub.3 is used to correct error generated by MDAC.sub.2 by adding b.sub.31 and b.sub.20. As illustrated, b.sub.21 is added to b.sub.10 to correct error generated by MDAC.sub.1. In general, therefore, b.sub.m1 is used to correct the error generated by MDACm.sub.m-1.
Still referring to FIGS. 1 and 2, each MDAC 18 has a 1.5 bit analog to digital converter (ADC) 36 for generating b.sub.1 and b.sub.0 from V.sub.I. Table 1 is a definition table for the values of b.sub.1 and b.sub.0 with respect to V.sub.I for the MDAC 18. It is noted that .+-.V.sub.r is the full scale range of the ADC 36.
TABLE 1 Input Voltage Range (V.sub.I) b.sub.1 b.sub.0 V.sub.I &lt; -V.sub.r /4 0 0 -V.sub.r /4 &lt; V.sub.I &lt; +V.sub.r /4 0 1 V.sub.I &gt; +V.sub.r /4 1 0
Once b.sub.1 and b.sub.0 are generated by the ADC 36 they are output at digital outputs 32, 34 and also input into a 1.5 bit digital to analog converter (DAC) 38. The DAC 38 converts b.sub.1 and b.sub.0 into an analog signal, or V.sub.DAC, used in the calculation of V.sub.res. Table 2 is a definition table for the value of V.sub.DAC with respect to b.sub.1 and b.sub.0 for the MDAC 18.
TABLE 2 b.sub.1 b.sub.0 V.sub.DAC 0 0 -V.sub.r /2 0 1 0 1 0 +V.sub.r /2
The MDAC 18 generates V.sub.res by subtracting V.sub.DAC from V.sub.I with an adder 40 and amplifying the summed value with an amplifier 42 having a gain of two. With additional reference to FIG. 3, the characteristics of the MDAC 18 are illustrated. FIG. 3 graphs V.sub.I versus V.sub.res and illustrates the values of b.sub.1 and b.sub.0 over the range of values for V.sub.I.
The last stage 30 is a two bit analog to digital converter (ADC) for converting the last stage's input voltage, V.sub.I, into a two bit digital value. Therefore, similar to the MDACs 18, the last stage has two digital outputs 32, 34 respectively providing b.sub.1 and b.sub.0. The b.sub.0 provided at the second digital output 34 for the last stage 30 represents the least significant bit of the digital output of the A/D converter 10. Alternatively, the last stage 30 can be implemented with an MDAC 18 without connecting the output 22 to any other stage. Table 3 is a definition table for the values of b.sub.1 and b.sub.0 with respect to V.sub.I for the two bit last stage 30.
TABLE 3 Input Voltage Range (V.sub.I) b.sub.1 b.sub.0 V.sub.I &lt; V.sub.r .multidot. 3/4 0 0 -V.sub.r .multidot. 3/4 &lt; V.sub.I &lt; -V.sub.r /4 0 1 -V.sub.r /4 &lt; V&lt; +V.sub.r /4 1 0 V.sub.I &gt; +V.sub.r /4 1 1
The digital outputs of the MDACs 18 and the last stage 30 are input into a digital logic correction circuit 44. The digital logic correction circuit 44 generates the digital output, D.sub.OUT, of the A/C converter 10. The digital output is a series of bits, or D.sub.N-1 to D.sub.0. In the example, N is four bits. Therefore, the digital output is D.sub.3, D.sub.2, D.sub.1 and D.sub.0 where D.sub.3 is the most significant bit (MSB) and D.sub.0 is the least significant bit (LSB). The digital logic correction circuit 44 corrects error caused by inaccurate thresholds in the 1.5 bit ADC 36 of the MDACs 18 and the two bit ADC of the last stage 30. As long as the individual thresholds deviate no more than V.sub.r /4 from an ideal value, then the error can be corrected by adding shifted digital outputs of each of the stages.
FIG. 4 depicts a shifting operation of the digital error correction circuit 44. It is noted that S is the number of stages of the A/D converter 10 excluding the SHA 14 and the last stage 30. In other words, S is the number of MDACs 18 in the pipeline AID converter 10.
FIG. 5 is a graph of the characteristics of the 4-bit A/D converter 10 illustrated in FIG. 1, under the condition that the thresholds for the 1.5 bit ADC 36 of the MDACs 18 and the 2 bit ADC of the last stage 30 deviate no more than V.sub.r /4. It is noted that .+-.V.sub.R is the full scale range of the A/D converter 10. It is also noted that an analog input voltage of zero volts is defined as the center of digital 1000. However, if the thresholds of the two bit ADC of the last stage 30 are +V.sub.r *3/4, +V.sub.r /4 and-V.sub.r /4, rather than the thresholds shown in Table 3, the A/D conversion curve illustrated in FIG. 5 will move one LSB to the right resulting in analog input voltage of zero volts being defined as the center of digital 0111.
Referring to FIGS. 2 and 13, the timing of the A/D converter 10 will be discussed. The A/D converter 10 has a bias and reference generator (not shown) and a clock generator (not shown). The bias and reference generator generates appropriate bias currents and voltage references for use by the various stages of the A/D converter 10. The clock generator generates a two phase non-overlapping clock signal, the respective clock pulse signals of which are referred to as CLK1 and CLK2. Waveformns for the two clock pulse signals, CLK1 and CLK2, are illustrated in the top portion of FIG. 13. CLK1 effectively has about a 50% duty cycle. CLK2 also effectively has about a 50% duty cycle but lags CLK1 by 180.degree..
As illustrated in FIG. 2, CLK1 is applied to a sample clock input SA of the SHA 14 and a hold clock input H of the amplifier 42 of MDAC.sub.1. CLK2 is applied to a hold clock input H of the SHA 14, a latch clock input L of the ADC 36 of MDAC.sub.1 and a sample clock input SA of the amplifier 42 of MDAC.sub.1. As indicated by FIG. 13, the same clock signals are used for MDAC.sub.2, :2.1 but the clock signals are alternated. More specifically, CLK1 is applied to the latch clock input L of the ADC 36 of MDAC.sub.2 and the sample clock input SA of the amplifier 42 of MDAC.sub.2 and CLK2 is applied to the hold clock input H of the amplifier 42 of MDAC.sub.2. If additional MDAC 18 stages are present for a higher resolution A/D converter IO, the third and subsequent MDACs 18 alternately use CLK1 and CLK2 for the sample/latch operation and the hold operation so that the sample/latch of the MDAC 18 coincides with the hold of the previous MDAC 18. CLK2 is applied to a latch clock input of the last stage 30. It is noted that the last stage 30 does not conduct sample and/or hold operations since the last stage 30 does not generate a residue output.
The sample, hold and latch operations of the SHA stage 14, MDAC.sub.1, MDAC.sub.2, and the last stage 30 are illustrated in the bottom portion of FIG. 13. The different shading in the timing diagram represents the pipeline conversion process on a series of two analog input samples as the samples pipeline through all of the stages. The SHA 14 samples the analog input signal, V.sub.IN, during CLK1 and conducts a hold operation during CLK2. MDAC.sub.1 samples V.sub.s/h during CLK2. The ADC 36 of MDAC.sub.1 operates during the pulse of CLK2 and preferably latches the digital output on the falling edge of CLK2, thereby giving V.sub.s/h time to settle to the analog equivalent of N bit accuracy. Therefore, the tolerance of the SHA 14 is the analog equivalent of one LSB. MDAC.sub.1 generates and holds the residue output V.sub.res1 during CLK1. MDAC.sub.2 samples V.sub.res1 during CLK1 and latches its digital output at the end of CLK1, or on the falling edge of CLK1, thereby giving V.sub.res time to settle to the analog equivalent of N-1 bit accuracy. MDAC.sub.2 generates and holds V.sub.res2 during CLK2. The last stage 30 latches its digital output at the end of CLK2, or on the falling edge of CLK2, thereby giving V.sub.res2 time to settle to the analog equivalent of N-2 bit accuracy.
Should additional information be desired regarding conventional pipeline A/D converters, attention is directed to Stephen H. Lewis et al., "A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter," IEEE J. Solid-State Circuits, vol. Sc-22, no. 6, pages 954-961, December 1987; Stephen H. Lewis et al., "A 10-b 20-Msample/s Analog-to-Digital Converter," IEEE J. Solid-State Circuits, vol. 27, no. 3, pages 351-358, March 1992; Thomas B. Cho et al., "A 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter," IEEE J. Solid-State Circuits, vol. 30, no. 3, pages 166-172, March 1995; Krishnaswamy Nagaraj et al., "A 250-mW, 8-b, 52-Msample/s Parallel-Pipelined A/D Converter with Reduced Number of Amplifiers, " IEEE J. Solid-State Circuits, vol. 32, no. 3, pages 312-320, March 1997; and Yuh-Min Lin et al., "A 13-b 2.5-MHZ Self-Calibrated Pipelined A/D Converter in 3-.mu.m CMOS, " IEEE J. Solid-State Circuits, vol. 26, no. 4, pages 628-636, April 1991, each of which are incorporated by reference in their entireties.
There is an ever present demand for A/D converters that accurately convert an analog voltage signal into a digital representation. An N bit A/D converter properly converts an analog voltage signal into a digital representation with N bit accuracy if the converter satisfies maximum differential non-linearity (DNL) and integral non-linearity (fNL) requirements. To achieve N bit resolution by the pipeline A/D converter structure exemplified in FIG. 1, V.sub.s/h needs to have the analog equivalent of N bit accuracy, V.sub.res1 needs to have the analog equivalent of N-1 bit accuracy, V.sub.res2 needs to have the analog equivalent of N-2 bit accuracy and so forth. However, it is difficult to achieve such accuracy for A/D converters having a high sampling rate (e.g., 25 MHZ and up) and a large number of output bits (e.g., N=8 and up).